ijustpostwhenimhi
425
12
0
Efficiency [--------|-]
Size? Any
Results:
Apologies to the symmetry fanatics, this layout is best for routing.
Haven't added the inductors here. Just 12vin and input caps for each phase's vin pin, plus general chip configuration wiring.
I'll need to isolate the inductors like I did for the 12v plane seen on the right. I've been using an xacto knife, but I've been considering other methods
tiderfish
Ok I read a few of your posts and am I intrigued. But what are you making? Or hope to accomplish?
ijustpostwhenimhi
I go into detail here /gallery/Qh9mtmn/comment/2450768631
charlie86
Still just curious... are you selecting the components and assembly method for fun? If the current load was to match the inductors, those traces on your BGA adapter PCB might not be strong enough...
ijustpostwhenimhi
Partly for fun, but also I wanted to reduce losses where I could, so having a very low resistance inductor was desired, and since size isn't an issue, I went overboard. This design is software assisted and that's what I'm referring to with the efficiency slider. These were suggested inductors required to meet the efficiency target (97%). The PCB design will be more reasonably sized. As for current limitations, the switch IC's 5w is balanced across 8 phases/traces before it reaches the load
weedeewee
Hey, Since you're digging into pcie switches I have a question you might be able to answer.
Is it possible to have a switch with a pcie4x4 upstream port and a pcie3x8 downstream port and use it at full pcie4x4 bandwidth ?
ijustpostwhenimhi
Yes. It's called bandwidth bridging. https://docs.broadcom.com/doc/bandwidth_bridge_using_pex_8604_v1.0_31mar10.pdf this is an older chip but the same concept applies to all generations.
weedeewee
Now to find a product that does what I need... :-/